1. Field of Invention
The present invention pertains to the field of circuit design. More particularly, this invention relates to low power circuit design through judicious module selection.
2. Art Background
Electronic circuits including integrated circuits such as application-specific integrated circuits (ASICS) may be employed in a wide variety of applications. The design process for relatively complex electronic circuits typically includes the generation of a behavioral specification of a circuit under design, the generation of a register transfer level (RTL) description from the behavioral description, and then the synthesis of a gate-level description from the RTL description.
A behavioral description usually characterizes a circuit under design as an arrangement of subsystems that perform desired functions. An RTL description usually specifies particular operations, such as add, multiply, shift, etc., that are to be performed during clock cycles of the circuit under design. A gate-level description usually provides the information necessary for fabrication of the circuit under design.
The process of generating an RTL description from a behavioral description usually includes the step of scheduling the operations that are to be performed during each clock cycle. A variety of modules are usually available for performing a scheduled operation. Therefore, the process of generating an RTL description from a behavioral description also usually includes the step of selecting which modules from the available modules are to be used perform the scheduled operations. Typically, the available modules differ according to one or more parameters.
Consider a design example in which a multiplication operation is scheduled for cycle n. One of a variety of available multiplier modules may be selected for use during cycle n according to the desired response. For example, the available multiplier modules may differ according to parameters such as resolution, rounding behavior, signed/unsigned operations, number of gates, etc.
Prior circuit design methods usually select modules in view of a set of design constraints. Such design constraints typically include a constraint on the overall gate count for the circuit under design and a constraint on the clock speed of the circuit under design. Unfortunately, prior techniques for circuit design usually do not provide a methodology for achieving low power consumption that enables tradeoffs between low power consumption and design constraints on the use of signed and unsigned modules together.
A circuit design system is disclosed that obtains low power circuit design through judicious module selection. The circuit design system implements methods that enable advantageous design tradeoffs between low power behavior and design constraints during module selection. The circuit design system selects unsigned modules which consume less power than signed modules where permitted in view of a desired response of a circuit and where advantageous for low power behavior while not violating the design constraints.
In one embodiment, the circuit design system selects an unsigned module for performing a scheduled operation in a circuit if permissible in view of a desired response of the circuit. If an existing signed module is appropriate for the scheduled operation, then the circuit design system selects an unsigned module for performing the scheduled operation if permissible in view of the desired response and if the unsigned module does not violate a set of design constraints for the circuit and uses the existing signed module otherwise. Otherwise, the circuit design system selects a signed module for performing the scheduled operation.
Other features and advantages of the present invention will be apparent from the detailed description that follows.